1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and, more specifically, to a semiconductor integrated circuit device having a voltage down converter for internally down converting an external power supply voltage to generate an internal power supply voltage. More specifically, the present invention relates to a structure for reliability evaluation test of a semiconductor integrated circuit device having an internal voltage down converter.
2. Description of the Background Art
As the storage capacity of a semiconductor device has been increased, MOS transistors (insulated gate type field effect transistors) constituting the memory device has been reduced in size. In view of reliability, high speed operation and lower power consumption of such miniaturized elements, lower operational power supply voltage is desirable. However, in a system employing such a semiconductor memory device, system power supply voltage is higher than the operational power supply voltage of such semiconductor memory device, in consideration of power supply voltages of processors and the like and compatability with memory devices of former generation. In order to generate an internal power supply voltage having a necessary voltage level for the semiconductor memory device from an external power supply voltage which is, for example, the system power supply voltage, a circuit called a voltage down converter is used for lowering the external power supply voltage and for supplying internal power supply voltage necessary for the memory operation in the semiconductor memory device. By using such a voltage down converter, power supply voltage of the semiconductor memory device is reduced and reliability of the device is ensured.
FIG. 20 schematically shows the overall structure of a conventional semiconductor integrated circuit. Referring to FIG. 20, a semiconductor memory device 900 is shown as an example of the semiconductor integrated circuit device. Semiconductor memory device 900 includes a voltage down converter 905 for lowering an external power supply voltage extVcc which is, for example, the system power supply voltage, to a prescribed voltage level to generate an internal power supply voltage intVcc on an internal power supply line 904, and a memory circuit 908 which operates using the internal power supply voltage intVcc on internal power supply line 904 and a ground voltage Vss applied through ground terminal 906 to a ground line 907 as both operational power supply voltages. Memory circuit 908 includes a plurality of memory cells each storing information and peripheral circuitry for accessing the memory cells.
By lowering external power supply voltage extVcc to generate internal power supply voltage intVcc using voltage down converter 905, it becomes possible to operate memory circuit 908 stably with low power consumption.
FIG. 21 schematically shows the structure of voltage down converter 905 shown in FIG. 20. Referring to FIG. 21, voltage down converter 905 includes a reference voltage generating circuit 905a generating a reference voltage Vref which has small dependency on external power supply voltage extVcc; a comparing circuit 905b which operates using power supply voltage extVcc on external power supply line 902 as one operational power supply voltage and compares the reference voltage Vref with the internal power supply voltage intVcc on internal power supply line 904; and a p channel MOS transistor 905c provided between external power supply line 902 and internal power supply line 904 for supplying current from external power supply line 902 to internal power supply line 904 in accordance with an output signal from comparing circuit 905b. Comparing circuit 905 consists of a differential amplifier receiving the internal power supply voltage intVcc at its positive input and reference voltage Vref at its negative input.
Voltage down converter 905 further includes a p channel MOS transistor 905d responsive to activation of a stress acceleration mode designating signal /STR for electrically connecting external power supply line 902 to Ian output node 905ab of reference voltage generating circuit 905a. The stress acceleration mode will be described later.
Stabilizing capacitors 909a and 909b for stabilizing voltages are provided for external power supply line 902 and internal power supply line 904, respectively. The operation will be briefly described in the following.
When internal power supply voltage intVcc is higher than the reference voltage Vref, the output signal of comparing circuit 905b is at an H level, p channel MOS transistor 905c is non-conductive, and current path from external power supply line 902 to internal power supply 904 is cut off.
Meanwhile, when internal power supply voltage intVcc is lower than the reference voltage Vref, the voltage level of the output signal of comparing circuit 905b lowers, conductance of p channel MOS transistor 905c increases and current is supplied from external power line 902 to internal power line 904. The conductance of p channel MOS transistor 905c increases as the difference between internal power supply voltage intVcc and reference voltage Vref increases. Accordingly, as the internal power supply voltage intVcc lowers, current is increasingly supplied from external power supply line 902 to internal power supply 904, and the lowered internal power supply voltage intVcc returns to the prescribed voltage level at high speed.
Therefore, the internal power supply voltage intVcc on internal power supply line 904 is maintained approximately at the voltage level of reference voltage Vref. The reference voltage Vref is at a constant voltage level not dependent on the external power supply voltage extVcc when stress acceleration mode designating signal /STR is at an inactive state of H level and p channel MOS transistor 905d is non-conductive. More specifically, by the feedback loop of comparing circuit 905b and p channel MOS transistor 905c, the internal power supply voltage intVcc is also kept at a constant voltage level.
The operation mode in which the stress acceleration mode designating signal /STR is set to the active state of L level will be described. The stress acceleration mode designating signal is activated at the time of burn in test, for example. The burn in test is performed for reliability evaluation of semiconductor integrated circuit devices. Generally, failures of semiconductor devices are classified into three periods, that is, initial failure period, accidental failure period and wear-out failure period, as time goes. The initial failure refers to a failure generated immediately after the start of use of the devices, which reveals potential defects existing at the time of manufacturing the semiconductor devices. The rate of initial failure rapidly decreases, followed by the accidental failure period in which low failure rate lasts long for a prescribed period. Near the end of useful life of the semiconductor devices, wear out failure period starts, in which failure rate increases abruptly. It is desired that the semiconductor devices are used in the accidental failure period, which corresponds to the actually reliable life.
Therefore, in order to enhance reliability of semiconductor integrated circuit devices, low failure rate of accidental failure and long lasting accidental failure period are desired. Meanwhile, it is necessary to screen out defective products having causes of initial failure to eliminate initial failure in advance, by performing aging acceleration operation for a prescribed time period on the semiconductor devices to reveal defects possibly causing initial failure. In order to effectively perform screening in a short period of time, it is desirable that the initial failure rate of the semiconductor devices decrease rapidly by screening so that the accidental failure period starts early. At present, high temperature operation test (burn in test) as stress acceleration test is performed as one method of screening. In the burn in test, semiconductor devices are operated continuously for several tens of hours to several days in high temperature environment, so as to directly evaluate reliability of gate insulating films of MOS transistors and dielectric films of memory cell capacitors of semiconductor memory devices, using semiconductor devices which are to be shipped as products, and any cause of defects including migration (electro migration and stress migration) of aluminum interconnection is revealed by applying stresses of high temperature and high electric field (high temperature/high voltage operating condition). The test is more effective when degree of acceleration is increased by operating semiconductor devices while the temperature is being increased.
For the screening, referring to FIG. 21, the stress acceleration mode designating signal /STR is set to the active state at the time of stress acceleration test, so that p channel MOS transistor 905b is rendered conductive and reference voltage Vref is set to the level of external power supply voltage extVcc. In this state, because of comparing circuit 905 and p channel MOS transistor 905c, internal power supply voltage intVcc attains to the level of the external power supply voltage extVcc, and therefore the external power supply voltage extVcc can be applied to the memory circuit in the semiconductor integrated circuit device. By making higher the voltage level of the external power supply voltage extVcc, the voltage can be accelerated, enabling effective screening test.
FIG. 22 schematically shows the structure of memory circuit 908 shown in FIG. 20. Referring to FIG. 22, memory circuit 908 includes: a memory cell array 908a having a plurality of memory cells arranged in a matrix; a row decoder 908b for decoding an internal row address signal applied from an address buffer (not shown) for driving the addressed row of memory cell array 908a to the selected state; a column decoder 908c for decoding an internal column address signal from an address buffer, not shown, in the similar manner, for generating a column selection signal for designating a column of memory cell array 908a; and sense amplifiers 908d each provided corresponding to each column of memory cell array 90a for sensing and amplifying memory cell data read on the corresponding column when activated. In memory cell array 908a, a word line is arranged corresponding to each row, and memory cells of the corresponding row are connected to the word line. Row decoder 908b drives the word line arranged corresponding to the addressed row to the selected state. In memory cell array 908a, a bit line pair is arranged for each column of memory cells, and the memory cells of the corresponding column are connected to the bit line pair. Column decoder 908c generates a signal for selecting a bit line pair arranged corresponding to the addressed column. Sense amplifier 908d includes a sense amplifier circuit provided corresponding to each bit line pair for differentially amplifying the memory cell data read on the bit line pair.
The memory circuit further includes a peripheral control circuit 908e for generating internal control signals necessary for various internal operations in accordance with externally applied row address strobe signal /RAS, column address strobe signal /CAS and write enable signal /WE. Row address strobe signal /RAS indicates the start of a memory cycle, and in response to activation (L level) of row address strobe signal /RAS, row decoding operation starts. Column address strobe signal /CAS designates the start of a column selecting operation, and in accordance with activation (L level) of column address strobe signal /CAS, the address buffer, not shown, generates and applies to column decoder 908c an internal column address signal. Write enable signal /WE indicates data writing operation, and when column address strobe signal /CAS and write enable signal /WE both attain to the active state of L level, data writing to the selected memory cell is performed internally.
FIG. 23 schematically shows a structure of a portion related to one column of the memory cell array shown in FIG. 20. Referring to FIG. 23, a memory cell MC arranged corresponding to a crossing between a bit line BL and a word line WL is shown as a representative. One row of memory cells are connected to the word line WL, and one column of memory cells are connected to a bit line pair BL and /BL. Memory cell MC includes a capacitor MQ storing information, and an access transistor MT consisting of an n channel MOS transistor responsive to a signal potential on the word line WL for connecting the memory capacitor MQ to the bit line BL.
The sense amplifier circuit included in sense amplifier 908d includes p channel MOS transistors P1 and P2 having their gates and drains cross coupled, and n channel MOS transistors N1 and N2 having their gates and drains cross coupled. More specifically, p channel MOS transistor P1 has its drain connected to bit line BL, and its gate connected to the bit line /BL. The p channel MOS transistor P2 has its drain connected to bit line /BL, and its gate connected to bit line BL. The sources of p channel MOS transistors P1 and P2 are coupled to internal power supply line 904a through a p channel MOS transistor P3 which is rendered conductive in response to activation (L level) of sense amplifier activating signal .phi.SP.
The n channel MOS transistor N1 has its drain connected to bit line BL, and its gate connected to bit line /BL.
The n channel MOS transistor N2 has its drain connected to the bit line /BL and its gate connected to the bit line BL. Sources of the n channel MOS transistors N1 and N2 are coupled to the ground line 907a through an n channel MOS transistor N3 which is rendered conductive when sense amplifier activating signal .phi.SN is activated (H level).
For the bit lines BL and /BL, an n channel MOS transistor N4 for electrically short-circuiting bit lines BL and /BL in response to a bit line equalize designating signal .phi.EQ, and n channel MOS transistors N5 and N6 which are rendered conductive in response to activation of the bit line equalize designating signal .phi.EQ for transmitting a precharge voltage Vb1 of a prescribed intermediate voltage level to bit lines BL and /BL are provided. The bit line equalize designating signal .phi.EQ attains to the active state of H level when the semiconductor memory device as the semiconductor integrated circuit device (hereinafter simply referred to as a semiconductor memory device) is at a standby state (when row address strobe signal /RAS is at the inactive state of H level).
In an active cycle (when signal /RAS is at the L level), bit line equalize designating signal .phi.EQ attains to the L level, and bit lines BL and /BL are set to the floating state at the voltage level of the prescribed precharge voltage Vb1. In this state, word line WL is selected and the stored data of memory cell MC is transmitted to bit line BL. Thereafter, sense amplifier activating signals .phi.SP and .phi.SN are activated, p channel MOS transistors P1 and P2 pull up one of the bit lines BL and /BL which is at a higher potential to the level of the internal power supply voltage intVcc on internal power supply line 904, while n channel MOS transistors N1 and N2 discharge the one of the bit lines BL and /BL which is at the lower potential, to the level of the ground voltage GND.
In this sensing operation, sensing operation of one row of memory cells connected to the selected word line WL of memory cell array 908a is performed. Therefore, a number of sense amplifier circuits operate simultaneously to charge/discharge respective bit line pairs. Therefore, much current is consumed during sensing operation of sense amplifiers 908d, and therefore it is a source of large current consumption as compared with other peripheral control circuit 908e, row decoder 908d and column decoder 908c.
In order to reduce power consumption of the semiconductor memory device, voltage level of internal power supply voltage intVcc generated from voltage down converter 905 is reduced. This makes smaller the voltage amplitude of the bit line pair, current consumption is reduced accordingly, and therefore power consumption can be reduced. However, voltage down converter 905 generates only one internal power supply voltage intVcc on internal power supply line 904. Accordingly, this low internal power supply voltage intVcc is also transmitted to the peripheral control circuit 908e, row decoder 908b and column decoder 908c as the peripheral circuitry. The MOS transistor has its speed of operation defined by the gate voltage (the drain current of MOS transistor is given as a square function of the gate voltage (when it operates in a saturation region)). Therefore, in this case, a semiconductor memory device operating at a high speed cannot be realized.
It may be possible to set higher the voltage level of internal power supply voltage intVcc and apply it to row decoder 908b, column decoder 908c, peripheral control circuit 908e and so on in order to realize high speed operation. However, in that case also, the internal power supply voltage intVcc which is made higher is applied to the sense amplifier 908d provided corresponding to each column of the memory cell array, voltage amplitude of each bit line increases, and therefore current consumption cannot be reduced.
Therefore, in the conventional semiconductor memory device, as it is provided with a voltage down converter generating only one internal power supply voltage, it has been difficult to realize high speed operation and low power consumption simultaneously.